How Chiplets are Helping to Democratize Semiconductor Design with Mohit Gupta, CEO of TYLsemi By Justin Kinsey, SBT & Mohit Gupta, TYLsemi August 17, 2026
Stop Guessing on Multi-Die PG Planning: Let AI Find the IR-Drop Sweet Spot By Soheil Modirzadeh August 13, 2026
What's New in UALink? Technical Deep Dive into the Latest UALink Specifications By Derek Williams (AMD), Dave Brown (AMD), Justin King (AMD), Arun Satyanarayana (Google) and Rob Pelt (AMD) August 6, 2026
Chiplets, RISC-V, and Europe's AI Silicon Ambition By Nandan Nayampally (Baya Systems) & Cesc Guim (Openchip) July 29, 2026
Driving the Future of Automotive Compute with UCIe By Bala Chavali, AMD & Ericles Sousa, Cadence July 27, 2026
A Physics-Informed Neural Network Surrogate for Runtime PDN and Dynamic Droop Prediction in 2.5-D Chiplet Integration By Xi Chen July 20, 2026
A Chiplet Interface Model for System-Level PPA Exploration By Austin Rovinski, New York University July 13, 2026
Zero trust in silicon: The new security imperative for chiplet-based 3D ICs By Tova Levy (Siemens) & Chris Jones (Crypto Quantique) July 2, 2026
Beyond the data pipe: Why connectivity IP is now the system-critical layer in every 3D IC By Tova Levy (Siemens EDA) & Archana Cheruliyil (Qualcomm) June 25, 2026
An Automated Interconnect Modeling Framework for Rapid Cryptolet Design Space Exploration By Austin Rovinski (NYU) June 24, 2026
DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation By Rashid Aligholipour June 22, 2026
Blueprint for AI Hardware But with Instructions: Pre-Validated Chiplet Building Blocks By Synopsys, Arm, AMI May 28, 2026
Standardizing System-Level Interoperability for Multi-Vendor Chiplets By Gilberto Rodríguez, Openchip & Fady Dahoud, GSOC May 22, 2026
Towards wafer-scale optical interconnect relying on Silicon Photonics and advanced 3D assembly By Peter Ossieur May 20, 2026
Pre-Silicon Chiplet Verification for Datacenters By Ravi Narayanaswami, Cadence & Marc Meunier, Arm May 18, 2026