Modeling, Optimizing and Exploring Multi-Die FPGA Routing Architectures By Amirhossein Poolad, University of Toronto June 5, 2026
A 32 Gb/s 0.41 pJ/bit Single-Ended Transmitter with TX-Based-Only Adaptive Crosstalk Cancellation for Ultra-Short-Reach Wireline Applications By Yixuan Shen, Institute of Microelectronics of the Chinese Academy of Sciences June 5, 2026
Transient Multiscale Workflow for Thermal Analysis of 3DHI Chip Stack By Mohammad Elahi, Rensselaer Polytechnic Institute June 2, 2026
Dispersion-Engineered Terahertz Silicon Interconnects Enabling Terabit-Scale Data Links By Bodhan Chakraborty, Nanyang Technological University June 1, 2026
Blueprint for AI Hardware But with Instructions: Pre-Validated Chiplet Building Blocks By Synopsys, Arm, AMI May 28, 2026
Standardizing System-Level Interoperability for Multi-Vendor Chiplets By Gilberto Rodríguez, Openchip & Fady Dahoud, GSOC May 22, 2026
Towards wafer-scale optical interconnect relying on Silicon Photonics and advanced 3D assembly By Peter Ossieur May 20, 2026
THz/RF Corridors as a General in-package Fabric For Chiplets, HBM, and High-speed Die-die Interconnect By Socionext April 14, 2026