Chiplet Technical Library

CHICO-Agent: An LLM Agent for the Cross-layer Optimization of 2.5D and 3D Chiplet-based Systems

By Qihang Wu, Arizona State University

April 22, 2026

A PPA-Driven 3D-IC Partitioning Selection Framework with Surrogate Models

By Shang Wang, University of Alberta

April 22, 2026

Fleet: Hierarchical Task-based Abstraction for Megakernels on Multi-Die GPUs

By Sangeeta Chowdhary, AMD Research

April 21, 2026

ChipLight: Cross-Layer Optimization of Chiplet Design with Optical Interconnects for LLM Training

By Kangbo Bai, Peking University

April 20, 2026

Tying Together Chiplets using Network-on-Chip

By Kent Orthner

April 16, 2026

Inside the AI Bottleneck: Data Movement, Chiplets, and System Scaling

By Nandan Nayampally

April 1, 2026

On-Package Chiplet Innovations with UCIe

By Debendra Das Sharma

March 26, 2026

Advanced Semiconductor Packaging Explained: Hybrid Bonding, Chiplets & Manufacturing Innovation

By TK Lee, Launch Tech

March 25, 2026

THz/RF Corridors as a General in-package Fabric For Chiplets, HBM, and High-speed Die-die Interconnect

By Socionext

April 14, 2026

In-Field Monitoring of Chiplets via ML-Driven On-Die Telemetry

By ProteanTecs

April 14, 2026

Chiplets for Automotive, Industrial, and Aerospace Applications

By Fraunhofer IIS

March 27, 2026

Designing the Future Today: AI-Driven Multi-Die Design

By Synopsys