Chiplet Technical Library

Location-Aware Caching Mechanism for minimizing performance degradation induced by inefficient inter-chiplet data path

By Jingyang Zheng, Fudan University

September 17, 2026

Predicting Cure Evolution and Thermal Endurance of a Highly Filled Epoxy Underfill for Advanced Packaging

By Ryan Giang, University of California San Diego

September 15, 2026

A Unified Interconnection Network for Chiplet-Based Scaling of the BrainScaleS Neuromorphic System

By Robin Heinemann, Heidelberg University

September 15, 2026

Fengshui: Demystifying Chiplet Ecosystem and Bespoke Neural Network Accelerator Codesign

By Haoran Jin, University of Michigan

September 11, 2026

Chiplet Identity and Roots of Trust in FCSA Systems: An Architecture-Agnostic Security View

By Mark Knight (Arm), Kent Chuang (PUFsecurity)

September 16, 2026

From Transistors to AI: The Chiplet Revolution with Ramune Nagisetty

By Amelia Dalton & Ramune Nagisetty

September 14, 2026

Scaling AI with Chiplets & CPO

By Dave Kulansky

September 11, 2026

Open Interconnect Innovations: A Deep Dive into the UALink Chiplet Specification Tutorial

By UALink and UCIe Consortia

September 7, 2026

THz/RF Corridors as a General in-package Fabric For Chiplets, HBM, and High-speed Die-die Interconnect

By Socionext

April 14, 2026

In-Field Monitoring of Chiplets via ML-Driven On-Die Telemetry

By ProteanTecs

April 14, 2026

Chiplets for Automotive, Industrial, and Aerospace Applications

By Fraunhofer IIS

March 27, 2026

Designing the Future Today: AI-Driven Multi-Die Design

By Synopsys