Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation
August 27, 2026
Chiplet Technical Papers
An Open-Source Benchmark Suite of 3D-IC Testcases
August 27, 2026
IC-ThermBench: An Open, Progressive Benchmark for Generalizable 2.5D/3D-IC Thermal Learning
August 26, 2026
Architecting the Next Generation of Asynchronous, Distributed GPUs for the AI Era
August 25, 2026
To Scale Up or To Scale Out: Evaluating Space-Time Costs of Compiled Logical Circuits on Modular Superconducting Quantum Processors
August 24, 2026
HYDRA: A Heterogeneous Chiplet DSE Framework for Serving Dynamic Hybrid LLM Workloads
August 21, 2026
Understanding and Profiling the Accelerator Chiplet Network Using PingPoint
August 14, 2026
C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconnect Architectures in LLM Cloud Computing Systems
August 12, 2026
ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.5D PIM Chiplet Architectures
August 11, 2026
Innovative FA hardware solution to enable system-level debug of 3D ICs
August 11, 2026
Hardware Design and Security in the Era of Chiplets and LLMs
August 6, 2026
DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation
July 28, 2026
APEX: an Adaptive Photonic-Electronic Chiplet Interconnection Architecture for DNN Inference
July 24, 2026
Formal Foundations for Known Good Reliable Die Screening in Chiplet-Based AI Systems-on-Chip
July 23, 2026
Optimization of Test-Access Architectures and Test Scheduling for 2.5D/3D Integration
July 23, 2026
Learning to Place Chiplets: A Multi-Objective Reinforcement Learning Approach
July 23, 2026
ThAME: 3D Memory-Enabled Heterogeneous Accelerator for LLM Mixture of Experts
July 21, 2026
Thermo-mechanical reliability evaluation and comparative fatigue assessment of 2.5D chiplet packages with viscoelastic C4 underfill
July 17, 2026
AI-Driven Thermal Mapping and Management in 3D Integrated Photonic Circuits
July 16, 2026
CLIP-3D: Closed-Loop Evaluation of Performance and Physical Constraints for 3D ICs
July 16, 2026
