Chiplet Technical Papers

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation

By Rashid Aligholipour, Uppsala University

July 28, 2026

APEX: an Adaptive Photonic-Electronic Chiplet Interconnection Architecture for DNN Inference

By Jingyi Chen, University of Science and Technology of China

July 24, 2026

Formal Foundations for Known Good Reliable Die Screening in Chiplet-Based AI Systems-on-Chip

By Prashanthi Metku, Qualcomm Technologies, Inc.

July 23, 2026

Optimization of Test-Access Architectures and Test Scheduling for 2.5D/3D Integration

By Ye Guo, Institute of Microelectronics of the Chinese Academy of Sciences

July 23, 2026

Learning to Place Chiplets: A Multi-Objective Reinforcement Learning Approach

By Richard Chang, Institute for Infocomm Research

July 23, 2026

ThAME: 3D Memory-Enabled Heterogeneous Accelerator for LLM Mixture of Experts

By Pratyush Dhingra, Washington State University

July 21, 2026

Thermo-mechanical reliability evaluation and comparative fatigue assessment of 2.5D chiplet packages with viscoelastic C4 underfill

By Peisheng Liu, Nantong University

July 17, 2026

AI-Driven Thermal Mapping and Management in 3D Integrated Photonic Circuits

By Liton Kumar Biswas, University of Florida

July 16, 2026

CLIP-3D: Closed-Loop Evaluation of Performance and Physical Constraints for 3D ICs

By Shuo Ren, Chinese University of Hong Kong

July 16, 2026

StreamDQ: Near-Memory Weight DeQuantization in Custom HBM for Scalable AI Inference Acceleration

By Minki Jeong, SK Hynix

July 15, 2026

HCRMap: Pressure-Aware Hot-Expert Residency Mapping for 3.5D MoE Chiplet Inference

By Yongqin Zhang, Nanjing Vocational College of Information Technology

July 14, 2026

Chiplet3D: Pin- and Thermal-Aware 3D Chiplet Floorplanning via Convolution-Embedded MILP

By Shuo Ren

July 14, 2026

The Signal-Integrity Control Strategy of a TSV Array for a Chiplet-Based System

By Bosen Wang, Xidian University

July 10, 2026

ThermoDSE: A Thermal-Aware and Comprehensive Design Space Exploration for Chiplet-Based DNN Accelerators

By Jian Peng, Hong Kong University of Science and Technology

July 9, 2026

GPU-Accelerated Effective Resistance Analysis for 3D IC Power Delivery Network

By Jingchao Hu, Zhejiang University

July 8, 2026

FAPlace: Joint Optimization of Chiplet Placement and Interposer Footprint for 2.5D Systems

By Yubo Hou, A*STAR

July 7, 2026

Chiplet-Escape: An Efficient Obstacle-Avoiding Escape Routing Method for Die-to-Die Interconnections in Chiplet-Based Designs

By WEIQING JI, University of Science and Technology Beijing

July 6, 2026

Shared timing resources for multiple chiplet interfaces

By Andres Ayes, University of Rochester

July 6, 2026

3DLS: A 3D Logic-Stacked Architecture for Disaggregated LLM Serving

By Jaehun Lee, KAIST

July 6, 2026

WarpagePINN: Thermal Warpage Prediction in Advanced Packaging via a Two-Stage Physics-Informed Neural Networks

By Xinyu Li, Shanghai University

July 2, 2026