Chiplets Modularity for AI and HPC

By Patricia González Guerrero, Lawrence Berkeley National Laboratory

Specialized computing and memory can drive a 1000x performance increase in High-Performance Computing (HPC). However, the cost of developing specialized hardware for HPC alone is prohibitive. As part of the Open Compute Project (OCP), we launched a new workstream, run by volunteers, to specify integration strategies to deliver specialization and heterogeneity for HPC and AI effectively. By streamlining chiplet modularity through open standards, we can significantly reduce the development costs of specialized hardware. These standards will facilitate the integration of chiplets from multiple vendors, promoting hardware IP reusability for both HPC and AI. We will define form factors and protocol standards and explore technologies that could accelerate scientific workloads. The ultimate goal is to produce a specification for standardized chiplet form factors and supporting technologies that enable seamless integration of chiplets and related hardware blocks into a System-in-Package (SiP), thereby unlocking the next generation of performance gains for scientific and engineering applications.

Bio

Dr. Patricia Gonzalez-Guerrero is a Research Scientist at Lawrence Berkeley National Laboratory. Her work spans ultra-low-power digital and mixed-signal SoC/ASIC/VLSI design for conventional and non-conventional forms of processing; Superconducting computing; Quantum readout and control; FPGAs/RISCV for exploration and evaluation of high-performance computing architectures; and hardware specialization through chiplets. She has three best paper awards, one best talk, two awarded patents and is currently co-leading the HPC&AI chiplets modularity workstream in the Open Compute Project.