Pre-Silicon Chiplet Verification for Datacenters

Presenters:

• Ravi Narayanaswami, Distinguished Engineer, Cadence Design Systems
• Marc Meunier, Director- HW Ecosystem, Arm

Data center companies are increasingly adopting chiplets to reduce schedule risk and rapidly deliver multi-die SoC and chiplet derivatives from a shared architectural baseline. In this joint talk- Cadence & Arm will showcase chiplet-based SoC development using pre-integrated- pre-verified building blocks to ensure interoperability with Cadence IP and remove months from SoC and chiplet development. 

Pre‑silicon chiplet verification is enabled using Arm's Foundation Chiplet System Architecture (FCSA)- aligned with OCP Open Chiplet Economy guidelines- leveraging simulation for early architectural interoperability assessment and multi‑vendor ecosystem collaboration. As part of the Arm Total Design ecosystem- we will also present a proof-of-concept emulation platform using Arm Neoverse™ CSS and Cadence® Design IP- including UCIe™ die-to-die links- memory (e.g.- LPDDR)- and IO fabrics (PCIe®- CXL)- demonstrating a practical path to validated chiplet system.