An Automated Interconnect Modeling Framework for Rapid Cryptolet Design Space Exploration

By Prof. Austin Rovinski (NYU)

State-of-the-art cryptographic hardware accelerators often require a huge amount of silicon area - sometimes even above the limit of what can fit onto a single chip. These accelerators motivate a shift to designing chiplet-based systems, where multiple chips are tightly integrated onto the same package instead of one large chip. However, chiplets also raise many new design constraints and tradeoffs in terms of packaging options, interconnect bandwidth, power, cost, and more. In this talk, I will present my group's recent work on developing an automated interconnect modeling framework which dramatically simplifies the process of modeling chiplet interconnects, and how it can be used to enable rapid, system-level design space exploration for cryptographic chiplet systems (cryptolets). I will also provide a sneak-peek demo of the framework before its open-source release next month.