DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation

By Rashid Aligholipour, Stefanos Kaxiras and Yuan Yao
Uppsala University

Scaling monolithic multicores is increasingly constrained by power/thermal limits, yield, and rising manufacturing and testing costs. Chiplet designs address these challenges by partitioning large dies into smaller parts (typically multiple core-complex dies and an I/O die) linked via high-bandwidth physical fabrics (PHY). As bandwidth and wiring density scale, however, these short-reach links are pushed closer to their signal-integrity limits, increasing susceptibility to noise, crosstalk, and channel loss, motivating stronger link-level reliability mechanisms such as forward error correction (FEC). Despite this trend, state-of-the-art simulation infrastructures often approximate inter-chiplet links using oversimplified, fixed-latency models. Such abstractions overlook the inherently dynamic, runtime-dependent behavior of the PHY—including channel conditions (e.g., signal-to-noise ratio shifts, signal crosstalk, clock jitter), iterative decoder convergence and packet retransmissions, and application dynamics (e.g., LLC-misses that travel across chiplet boundaries)—all of which are hard to determine offline. We show that neglecting these effects distorts inter-chiplet packet-level timing and high-level performance metrics such as IPC, leading to off-trend simulation results. 

We present DICE, an in-simulation, runtime PHY modeling in gem5 that captures the end-to-end inter-chiplet datapath, including QC-LDPC encoding/decoding, PAM4 modulation, lossy-channel transmission, LLR-based demodulation, adaptive packet re-sending, and PHY-level flow control between chiplets. For fidelity, we calibrate component latencies via hardware synthesis (e.g., QC-LDPC decode paths and iteration budgets) and compare the integrated system against production chiplet processors. Compared with state-of-the-art fixed-latency inter-chiplet links such as HeteroGarnet, DICE reshapes packet-latency composition and shifts system IPC by an average of 6.8% and up to 27.6%, revealing variability driven by realistic PHY link behaviors, enabling more accurate co-evaluation of performance, reliability, and design trade-offs in modern chiplet systems.