A Chiplet Interface Model for System-Level PPA Exploration
By Austin Rovinski, Assistant Professor, New York University
State-of-the-art cryptographic hardware accelerators often require a huge amount of silicon area, sometimes exceeding what can fit on a single chip. This motivates chiplet-based systems, where multiple chips are tightly integrated in one package instead of relying on one large die. In this talk, Austin Rovinski will present recent work on an automated interconnect modeling framework that simplifies chiplet interconnect modeling and enables rapid, system-level design space exploration for generic chiplet systems. A demonstration of the framework will follow later in the session.
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