Zero trust in silicon: The new security imperative for chiplet-based 3D ICs

By Tova Levy

“You don’t just say, the other chiplet that’s on this die, I’m going to trust it, it’s fine. No — moving forward with these kind of technologies, you need to actually challenge the other dies and make them prove that they are who they say they are.”
Chris Jones, Director of Applications at Crypto Quantique

How do you secure a chip when the chip itself is made up of dies from multiple vendors and you can’t automatically trust any of them?

In this episode of the Siemens 3D IC Podcast, host Tova Levy speaks with Chris Jones, Director of Applications at Crypto Quantique, about what it takes to build hardware security into silicon from the ground up — and why the move to 3D IC architectures makes that challenge dramatically harder.

Chris opens by explaining what hardware security actually means at the silicon level: not just encryption, but a fixed, immutable boot sequence that runs from ROM every time a device powers on, verifying that firmware is signed and untampered before any application code is allowed to execute. It’s a foundation that must be designed in not bolted on after the fact.
When chiplets from multiple vendors are stacked in a single package, every die-to-die interface becomes a potential attack surface. Chris explains why the industry must adopt a zero trust model — no chiplet should be assumed trustworthy simply because it’s in the stack — and how physically unclonable functions (PUFs) enable each die to cryptographically prove its identity without ever exposing a secret key.

Chris and Tova also explore the industry forces pushing security up the agenda: the Trusted Computing Group and GlobalPlatform standardizing hardware roots of trust; NIST maintaining verified cryptographic standards; and the EU Cyber Resilience Act, requiring built-in security, OTA updates, and documented risk analysis for all connected products by December 2027.

The episode closes with the joint solution Crypto Quantique has developed with Siemens: QRoot Lite, a lightweight root-of-trust IP block now integrated into Siemens’ Tessent EDA toolchain, automatically securing IJTAG-based DFT interfaces during manufacturing and ensuring test sequences can only be run by authorized parties. Find the full case study here.

For anyone working in 3D IC design, chiplet architecture, semiconductor security, or EDA, this episode offers a grounded, practical view of what it means to take hardware security seriously — from the first blank sheet of paper all the way through manufacturing.

• (02:00) Chris’s background: 30 years of all-round experience
• (03:00) What is hardware security? 
• (05:30) Why hardware security is critical now & examples of security breaches
• (08:30) Current security practices and required changes
• (08:27) How security has traditionally been done — and what has to change
• (11:13) The shift to a system-level view of security, especially in chiplet-based design
• (11:00) Security challenges in 3D IC architectures 
• (12:30) How can companies maintain IP integrity and prevent tampering throughout the 3D IC lifecycle?
• (15:30) Maintaining IP integrity in 3D IC supply chains
• (17:40) The Crypto Quantique / Siemens joint solution
• (20:11) The most important thing designers and system architects should understand about hardware security.