Blueprint for AI Hardware But with Instructions: Pre-Validated Chiplet Building Blocks
Synopsys, Arm, and AMI discuss deploying chiplet systems at scale. In this video, leaders explain how IP, firmware, and interconnect standards must align to enable practical architectures for AI, automotive, and HPC designs.
Speakers
- Frank Schirrmeister, Executive Director, Product Management, Synopsys
- Marc Meunier, Director of Ecosystem Developement, Arm
- Sanjoy Maity, Chief Executive Officer, AMI
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
Related Videos
- Standards for Chiplet Design with 3DIC Packaging (Part 1)
- Standards for Chiplet Design with 3DIC Packaging - Part 2
- Intel Demonstrates First Fully Integrated Optical I/O Chiplet for More Scalable AI
- Driving AI Innovation with Chiplet Standards
Latest Videos
- Accelerating Chiplet SoC Development with Standards-Based Frameworks and Automated Design Flows
- Qualcomm's Tony Pialis on Dragonfly and the Data Movement Wall
- From silos to system: Sujit Sharan on the cultural and technical shift 3D IC demands
- Advancing 3DIC Technologies to Propel AI Innovations
- Building Real Confidence in Chiplet Stacks with Evelyn Landman of proteanTecs