GPU-Accelerated Effective Resistance Analysis for 3D IC Power Delivery Network
July 8, 2026
Chiplet Technical Papers Archive - Page 2 of 15
FAPlace: Joint Optimization of Chiplet Placement and Interposer Footprint for 2.5D Systems
July 7, 2026
Chiplet-Escape: An Efficient Obstacle-Avoiding Escape Routing Method for Die-to-Die Interconnections in Chiplet-Based Designs
July 6, 2026
Shared timing resources for multiple chiplet interfaces
July 6, 2026
3DLS: A 3D Logic-Stacked Architecture for Disaggregated LLM Serving
July 6, 2026
WarpagePINN: Thermal Warpage Prediction in Advanced Packaging via a Two-Stage Physics-Informed Neural Networks
July 2, 2026
A Comprehensive Design Framework for Vertical Power Delivery in High-Performance Computing
June 30, 2026
SHIFT: Dynamic Compute Relocation Framework for Communication-Aware Chiplet-Based Systems
June 30, 2026
Failure Analysis in Transition: An Industry Survey of Challenges, Priorities, and Standardization Needs in Advanced Packaging and Heterogeneous Integration
June 23, 2026
2.5D Root of Trust: Securing the Chiplet Ecosystem
June 23, 2026
Plasma Etch Process Optimization for Photonic-Grade Diamond-on-Insulator Substrates and Thickness Evaluation using Colorimetry
June 19, 2026
CUTh-Solver: GPU-Accelerated Sparse Matrix Solver for High-Resolution Thermal Simulation of 3D ICs
June 18, 2026
Making Locality-aware GEMM Compatible with Page-Granularity Placement on Chiplet GPUs
June 11, 2026
Advanced semiconductor packaging design via artificial intelligence and machine learning: A review
June 9, 2026
DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective
June 8, 2026
Modeling, Optimizing and Exploring Multi-Die FPGA Routing Architectures
June 5, 2026
A 32 Gb/s 0.41 pJ/bit Single-Ended Transmitter with TX-Based-Only Adaptive Crosstalk Cancellation for Ultra-Short-Reach Wireline Applications
June 5, 2026
Transient Multiscale Workflow for Thermal Analysis of 3DHI Chip Stack
June 2, 2026
Dispersion-Engineered Terahertz Silicon Interconnects Enabling Terabit-Scale Data Links
June 1, 2026
Design-Oriented Modeling of TSV Substrate Noise Coupling to Ring VCOs
May 29, 2026
