Chiplet Technical Papers Archive - Page 2 of 17

CHIPSMORE: Compute-in-Interconnect and -Memory Chiplets for Multi-Mode Multi-Request LLM Inference Acceleration

By Yue Jiet Chong, National University of Singapore

September 1, 2026

ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI

By Chetan Choppali Sudarshan, Arizona State University

August 31, 2026

Generative Design of Liquid-Cooling Channels for Thermal Management of 2.5D and 3D Integrated Advanced Packaging

By Michael Acquah, University of Michigan-Dearborn

August 31, 2026

Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation

By Seongwon Yoon, Georgia Institute of Technology

August 27, 2026

An Open-Source Benchmark Suite of 3D-IC Testcases

By Rohan Soni, University of California

August 27, 2026

IC-ThermBench: An Open, Progressive Benchmark for Generalizable 2.5D/3D-IC Thermal Learning

By David Huang, University of Technology Sydney

August 26, 2026

Architecting the Next Generation of Asynchronous, Distributed GPUs for the AI Era

By Junrui Pan, Purdue University

August 25, 2026

To Scale Up or To Scale Out: Evaluating Space-Time Costs of Compiled Logical Circuits on Modular Superconducting Quantum Processors

By Nikiforos Paraskevopoulos, Dark Qore

August 24, 2026

HYDRA: A Heterogeneous Chiplet DSE Framework for Serving Dynamic Hybrid LLM Workloads

By Jiahao Lin, University of Wisconsin–Madison

August 21, 2026

Understanding and Profiling the Accelerator Chiplet Network Using PingPoint

By Junyeol Ryu, University of Wisconsin–Madison

August 14, 2026

C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconnect Architectures in LLM Cloud Computing Systems

By Jiayi Li, Peking University

August 12, 2026

ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.5D PIM Chiplet Architectures

By Vibhanshu Sharma, Washington State University

August 11, 2026

Innovative FA hardware solution to enable system-level debug of 3D ICs

By Lesly Endrinal, Google LLC

August 11, 2026

Hardware Design and Security in the Era of Chiplets and LLMs

By Johann Knechtel, NYU Abu Dhabi

August 6, 2026

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation

By Rashid Aligholipour, Uppsala University

July 28, 2026

APEX: an Adaptive Photonic-Electronic Chiplet Interconnection Architecture for DNN Inference

By Jingyi Chen, University of Science and Technology of China

July 24, 2026

Formal Foundations for Known Good Reliable Die Screening in Chiplet-Based AI Systems-on-Chip

By Prashanthi Metku, Qualcomm Technologies, Inc.

July 23, 2026

Optimization of Test-Access Architectures and Test Scheduling for 2.5D/3D Integration

By Ye Guo, Institute of Microelectronics of the Chinese Academy of Sciences

July 23, 2026

Learning to Place Chiplets: A Multi-Objective Reinforcement Learning Approach

By Richard Chang, Institute for Infocomm Research

July 23, 2026

ThAME: 3D Memory-Enabled Heterogeneous Accelerator for LLM Mixture of Experts

By Pratyush Dhingra, Washington State University

July 21, 2026