DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective

By Yang Xiang ¹, Zhuo Chen ¹, Nicolò Ronchi ¹, Arvind Sharma ¹, Fernando García-Redondo ², Subhali Subhechha ¹, Attilio Belmonte ¹, Maarten Rosmeulen ^1,3, Gouri Sankar Kar ¹, Dwaipayan Biswas ¹, Jan Van Houdt ^1,4
1 imec, Leuven, 3001 Belgium 
² imec, Cambridge, CB1 2JD U.K. 
³ Department of Electrical Engineering, KU Leuven, Leuven, 3001 Belgium 
⁴ Department of Physics and Astronomy, KU Leuven, Leuven, 3001 Belgium

Abstract

InGaZnO (IGZO)-channel FeFETs have attracted notable interest thanks to recent advances in endurance, opening up their application space for read-dominated AI memory tiers. This work evaluates the viability of NOR-type IGZO FeFETs for 3D heterogeneous AI memories from a read-centric design-technology co-optimization (DTCO) perspective, spanning on-chip back-end-of-line (BEOL) RAMs and hybrid-bonded memory chiplets, and off-chip, monolithically integrated 3D FeNOR storage-class memories (SCMs). For on-chip BEOL RAMs and memory chiplets, we demonstrate the cross-node bitcell footprint scalability of IGZO FeFETs capable of delivering down to 10-A SRAM-equivalent bitcell area (∼0.016 µm²) with 7-nm ground rules while maintaining a sub-5 ns random access latency -- despite their writability challenges. We further identify the sensing margin penalty in NOR FeFET arrays arising from sneak current associated with the negative program-state V_t, which requires positive-V_t engineering in order to eliminate the unwanted negative voltage read inhibition -- for example, by ferroelectric layer thinning. Last but not least, we elucidate the read margin implications on 3D FeNOR for SCMs, with the 3D stacking density limited by additional sneak current from neighbor channel shunting.

Index Terms: NOR FeFET, DTCO, BEOL RAM, Memory Chiplet, Storage Class Memory (SCM).

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