A 32 Gb/s 0.41 pJ/bit Single-Ended Transmitter with TX-Based-Only Adaptive Crosstalk Cancellation for Ultra-Short-Reach Wireline Applications
By Yixuan Shen 1,2, Zexin Su 1, Chang Liu 1,2,Xiao Ma 1, Lei Wang 1 and Bo Li 1,2
1 Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
2 University of Chinese Academy of Sciences, Beijing 100049, China

Abstract
Driven by the rapid advancement of artificial intelligence (AI) workloads, the demand for high-bandwidth and energy-efficient die-to-die (D2D) wireline communication has significantly increased. The article presents an original lumped-parameter model for the analysis of ultra-short-reach (USR) channels in D2D links. The model leads to a length-dependent crosstalk theory showing that the far-end crosstalk (FEXT) and near-end crosstalk (NEXT) exhibit approximately identical waveform amplitudes and pulse widths, differing only in polarity. Based on the property, a 32 Gb/s single-ended transmitter (TX) incorporating a TX-based-only adaptive crosstalk cancellation (XTC) scheme is presented. The proposed scheme eliminates receiver-side FEXT sensing, thereby simplifying calibration logic and reducing power consumption. Implemented in 28 nm CMOS, post-layout simulations demonstrate an energy efficiency of 0.41 pJ/bit at 32 Gb/s and more than 60% reduction in crosstalk-induced jitter (CIJ) across channel lengths of 0.5–2 mm and pitches of 5–20 µm.
Keywords: crosstalk cancellation (XTC); feed-forward equalizer (FFE); signal integrity (SI); single-ended; wireline transmitter (TX)
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