Shared timing resources for multiple chiplet interfaces

By Andres Ayes & Eby G. Friedman
University of Rochester, NY, USA

Abstract

Heterogeneous systems require robust and universal interfaces for die-to-die communication. Industry communication protocols, such as UCIe and Bunch of Wires, provide robust, high bandwidth die-to-die communication for a wide range of technologies. These interfaces include dedicated delay locked loops (DLLs), duty cycle correctors, and deskew circuits at each interface to ensure timing reliability. As the number of dies, or chiplets, within these systems grows, the number of heterogeneous interfaces increases, requiring significant resources. A shared timing approach is presented, where a set of timing circuits provides a clock signal for multiple interfaces, reducing the need for additional circuitry. Clock signal inversion substitutes for the DLLs within the single data rate interfaces to provide a temporal shift to improve reliability. The accumulated jitter along the clock signal path as the signal traverses multiple interfaces is quantified for a 7 nm CMOS process technology. Each interface contributes 2 to 5 ps of RMS jitter. This shared timing approach can be adopted for physically close interfaces with low bandwidth requirements and high noise tolerance to remove the need for DLLs and DCCs at each interface.

To read the full article, click here