3DLS: A 3D Logic-Stacked Architecture for Disaggregated LLM Serving

By Jaehun Lee, In-Jun Jung, Joo-Young Kim
KAIST, South Korea

Abstract

Large language model (LLM) serving increasingly combines prefill-decode (PD) disaggregation with tensor parallelism (TP) to support large models and long contexts. In conventional 2D/2.5D chiplet architectures, layer-wise prefill-todecode KV-cache transfer decode-side TP collectives share the same lateral die-to-die (D2D) interconnect, creating mixed-traffic contention on the decode critical path. This contention increases communication latency, prolongs token generation intervals, and degrades end-to-end serving performance. We propose 3DLS, a logic-on-logic 3D-stacked chiplet architecture that separates traffic classes by routing KV-cache transfers through vertical interconnects while preserving decode-side TP collectives on the lateral D2D fabric. 3DLS achieves up to 1.49× throughput and 60.2% lower end-to-end (E2E) latency over the shared-fabric planar baseline, and still achieves up to 1.17× throughput and 31.4% lower E2E latency over a workload-aware priority-managed planar baseline. These results highlight that physical isolation is an important design principle for future chiplet-based PD-disaggregated LLM serving systems.

Index Terms—Large Language Model, LLM Serving, Disaggregated Serving, Chiplet, KV cache, 3D integration.

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