APEX: an Adaptive Photonic-Electronic Chiplet Interconnection Architecture for DNN Inference

By Jingyi Chen, Mengke Ge, Haocai Luo, Hexiang Liu, Song Chen
University of Science and Technology of China, Hefei, China

Abstract

The exponential growth of Deep Neural Network (DNN) has precipitated a crisis in inter-chiplet communication, where traditional electrical interconnects struggle to meet the bandwidth density and energy efficiency requirements of massive-scale inference. While Silicon Photonics (SiPh) inherently offers the high bandwidth density and distance-independent energy efficiency required to transcend these metallic barriers, existing optical architectures remain fundamentally constrained by static topologies and prohibitive thermal reconfiguration latencies. This rigidity renders them ill-suited for the dynamic, phase-varying traffic patterns inherent in DNN workloads. To this end, we introduce APEX, a reconfigurable photonic-electrical interconnection architecture with dynamic logical topology reconfiguration algorithm engineered to resolve these scalability barriers. Central to APEX is a novel state-aware randomized greedy heuristic algorithm, which dynamically orchestrates wavelength allocation to adapt to the phase-varying traffic patterns inherent in DNN workloads. We validate the proposed approach against an optimal Integer Linear Programming (ILP) baseline, demonstrating that our linear time heuristic achieves near-optimal fidelity with a marginal energy overhead of only 5.6% in the early stages. Furthermore, it demonstrates robust scalability to synthesize full-layer network configurations where ILP solvers face combinatorial explosion. Evaluation across representative workloads reveals that APEX delivers a substantial leap in energy efficiency, achieving 0.69 pJ/bit for the BERT model—an approximate 41% reduction compared to Simba’s 1.17 pJ/bit.

Keywords: Chiplet, photonic-electrical interconnect, DNN Inference, accelerator

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