CLIP-3D: Closed-Loop Evaluation of Performance and Physical Constraints for 3D ICs

By Shuo Ren, Libo Shen, Yaohui Han, Leilei Jin, Chenghan Wang, Zhen Zhuang, Rongliang Fu, Bei Yu, Tsung-Yi Ho
Chinese University of Hong Kong

Abstract

3D integration packs more power into a smaller footprint, so a candidate design’s actual throughput depends on its layout: which macro sits on which tier, where the hot spot lands, and how cache geometry maps to access cycles. Architectural simulators like gem5 report IPC under idealized timing. They do not produce the per-block power map, the cache cycle counts, or the 3D layout that decide the realized billion-instructions-per second (BIPS), so early-stage 3D-IC exploration selects designs without accounting for the effects that decide whether they throttle on silicon. We present CLIP-3D, a shift-left flow that exposes 3D layout-driven thermal, wire, and cache effects to early-stage architectural exploration before any sign-off tool is invoked. The first stage lifts an architectural configuration into a physical block representation: McPAT for per-block dynamic and leakage power, CACTI for cache geometry and access cycles, and a HotSpot-compatible 3D stack discretization. The second stage runs an analytical 3D thermal-aware floorplanner over that representation. The floorplanner objective embeds a closed-form sustained-frequency expression derived from the linearity of HotSpot’s steady-state operator and the standard CMOS power frequency decomposition. Cross-tier macro assignment and in plane placement are co-optimized for the realized BIPS rather than for a half-perimeter wirelength (HPWL)-plus-temperature surrogate with hand-tuned weights. On an 80-configuration ar chitecture sweep under stressed cooling, the floorplanner delivers a realized BIPS gain of 13.75% on average (max 24.77%) over the shelf-pack baseline on every one of the 48 thermally-binding configurations and a wire-driven 5.82% on average on the 32 headroom configurations, when each method’s optimized layout is back-annotated into gem5 to capture layout-conditional cache and wire latency. The same realized BIPS plateau is reached by a cool3d-canonical baseline and an SA-plus-𝜆-mix grid-search baseline at 2.0× and 2.9× more wall time respectively, so in these experiments CLIP-3

Index Terms — 3D ICs, architecture evaluation, physical constraints, thermal throttling, design space exploration

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