AI-Driven Thermal Mapping and Management in 3D Integrated Photonic Circuits
By Liton Kumar Biswas 1, Katayoon Yahyaei 1, Shajib Ghosh 1, M Shafkat M Khan 1, Himanandhan Reddy Kottur 1, Rayhane Ghane-Motlagh 2, Mahdi Nikdast 3, Navid Asadizanjani 1
1 University of Florida, Gainesville, Florida 32611
2 ficonTEC Service USA Inc., FL, USA
3 Colorado State University, Fort Collins, Colorado 80523

Abstract
Photonic Integrated Circuits (PICs) are advancing high-performance computing, data centers, and sensing, yet three-dimensional (3D) PICs introduce critical thermal management challenges due to high-density bonding and heterogeneous materials. Traditional methods like thermal microscopes and in-package sensors yield sparse data, limiting full thermal profile visibility. This paper presents a dual-method solution combining an AI-driven thermal modeling framework with a design-based heuristic approach. The AI method integrates sparse sensor data with design layer and density information to predict multilayer temperature variations, while the heuristic approach uses localized material properties, design layout, component geometries, and sensor coordinates to refine thermal estimations in specific regions. A 2D thermal map of a 3D PIC is generated by interpolating sensor data and adjusting for local thermal resistivity using comparative analysis between design regions. The heuristic method complements the AI model, improving estimation accuracy without extensive training data. Together, these methods offer a scalable, accurate solution for real-time thermal mapping and design-time simulation, enabling reliable thermal management in next-generation 3D photonic systems.
To read the full article, click here
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Technical Papers
- The Evolution of Photonic Integrated Circuits and Silicon Photonics
- 3D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency
- Advances in waveguide to waveguide couplers for 3D integrated photonic packaging
- Monolithically Integrated Optical Through-Silicon Waveguides for 3D Chip-to-Chip Photonic Interconnects
Latest Technical Papers
- AI-Driven Thermal Mapping and Management in 3D Integrated Photonic Circuits
- CLIP-3D: Closed-Loop Evaluation of Performance and Physical Constraints for 3D ICs
- StreamDQ: Near-Memory Weight DeQuantization in Custom HBM for Scalable AI Inference Acceleration
- HCRMap: Pressure-Aware Hot-Expert Residency Mapping for 3.5D MoE Chiplet Inference
- Chiplet3D: Pin- and Thermal-Aware 3D Chiplet Floorplanning via Convolution-Embedded MILP