Optimization of Test-Access Architectures and Test Scheduling for 2.5D/3D Integration
By Ye Guo 1,2, Yan Feng 1, Zhiqiang Li 1, Guanfei Gong 1, Sumin Fan 1,2, Xu Sun 1 and Xiaolin Tang 1,2
1 Institute of Microelectronics of the Chinese Academy of Sciences, China
2 University of Chinese Academy of Sciences, China
Abstract
Test access mechanism (TAM) design is crucial for test efficiency in 2.5D/3D integrated circuits. This paper proposes a flexible and reconfigurable scan chain generation method to optimize TAM resources in 2.5D/3D integrated circuits. The method innovatively introduces a grid-based power-aware test architecture that enables dynamic scan chain reconfiguration, allowing cores to be flexibly allocated into different scan chains for optimal test scheduling. A mathematical model is developed to optimize scan chain configurations and their test schedules. Experimental results on the ITC'02 benchmark circuits demonstrate that the proposed method achieves up to 27.1% reduction in test time and up to 37.39% improvement in TAM utilization compared with the existing robust optimization approach. Moreover, it provides a more flexible and scalable test architecture for 2.5D/3D ICs.
Keywords: 2.5D/3D IC testing, test scheduling, TAM optimization Classification: Integrated circuits
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