Optimization of Test-Access Architectures and Test Scheduling for 2.5D/3D Integration
By Ye Guo 1,2, Yan Feng 1, Zhiqiang Li 1, Guanfei Gong 1, Sumin Fan 1,2, Xu Sun 1 and Xiaolin Tang 1,2
1 Institute of Microelectronics of the Chinese Academy of Sciences, China
2 University of Chinese Academy of Sciences, China
Abstract
Test access mechanism (TAM) design is crucial for test efficiency in 2.5D/3D integrated circuits. This paper proposes a flexible and reconfigurable scan chain generation method to optimize TAM resources in 2.5D/3D integrated circuits. The method innovatively introduces a grid-based power-aware test architecture that enables dynamic scan chain reconfiguration, allowing cores to be flexibly allocated into different scan chains for optimal test scheduling. A mathematical model is developed to optimize scan chain configurations and their test schedules. Experimental results on the ITC'02 benchmark circuits demonstrate that the proposed method achieves up to 27.1% reduction in test time and up to 37.39% improvement in TAM utilization compared with the existing robust optimization approach. Moreover, it provides a more flexible and scalable test architecture for 2.5D/3D ICs.
Keywords: 2.5D/3D IC testing, test scheduling, TAM optimization Classification: Integrated circuits
To read the full article, click here
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Technical Papers
- ATSim: A Fast and Accurate Simulation Framework for 2.5D/3D Chiplet Thermal Design Optimization
- Development and Optimization of Fine-Pitch RDL for RDL Interposer, and Embedded Bridge Die Interposer Fabrication Using Fan-Out Wafer-Level Packaging Technology
- CHICO-Agent: An LLM Agent for the Cross-layer Optimization of 2.5D and 3D Chiplet-based Systems
- Wafer Warpage of Silicon Interposer in Manufacturing Processes for High Density 2.5D Advanced Packaging: Causes, Measurement, Analysis and Optimization
Latest Technical Papers
- Formal Foundations for Known Good Reliable Die Screening in Chiplet-Based AI Systems-on-Chip
- Optimization of Test-Access Architectures and Test Scheduling for 2.5D/3D Integration
- Learning to Place Chiplets: A Multi-Objective Reinforcement Learning Approach
- ThAME: 3D Memory-Enabled Heterogeneous Accelerator for LLM Mixture of Experts
- Thermo-mechanical reliability evaluation and comparative fatigue assessment of 2.5D chiplet packages with viscoelastic C4 underfill