Chiplet Technical Papers Archive - Page 2 of 10

HALO: Memory-Centric Heterogeneous Accelerator with 2.5D Integration for Low-Batch LLM Inference

By Shubham Negi, Purdue University

October 6, 2025

Chiplet-Based RISC-V SoC with Modular AI Acceleration

By P. Ramkumar, American University of Sharjah

September 25, 2025

Near-energy-free photonic Fourier transformation for convolution operation acceleration

By Hangbo Yang, University of Florida

September 23, 2025

Optimizing Inter-chip Coupler Link Placement for Modular and Chiplet Quantum Systems

By Zefan Du, Fordham University

September 15, 2025

Material Needs and Measurement Challenges for Advanced Semiconductor Packaging: Understanding the Soft Side of Science

By Ran Tao, NIST

September 13, 2025

Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges

By Peng Gu, University of California

September 8, 2025

MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging

By Jinwei Tang, University of Minnesota

August 29, 2025

ATSim: A Fast and Accurate Simulation Framework for 2.5D/3D Chiplet Thermal Design Optimization

By Qipan Wang, Peking University

August 29, 2025

Chiplet-Based Architectures: Redefining the Future of System-on-Chip (SoC) Design

By Hameed Ul Hassan Mohammed, ProteanTecs

August 22, 2025

AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems

By Ishraq Tashdid, University of Central Florida

August 20, 2025

THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures

By Alish Kanani, University of Wisconsin–Madison

August 19, 2025

LaZagna: An Open-Source Framework for Flexible 3D FPGA Architectural Exploration

By Ismael Youssef, Georgia Institute of Technology

August 18, 2025

Corsair: An In-memory Computing Chiplet Architecture for Inference-time Compute Acceleration

By Satyam Srivastava, d-Matrix Corporation

August 11, 2025

Thermal Implications of Non-Uniform Power in BSPDN-Enabled 2.5D/3D Chiplet-based Systems-in-Package using Nanosheet Technology

By Yukai Chen, IMEC

August 6, 2025

Chiplets Are The New Baseline for AI Inference Chips

By Sid Sheth, d-Matrix Corp

August 5, 2025

Hybrid Bonding With Polymeric Interlayer Dielectric Layers Patterned by Nanoimprint Lithography

By Sungwoo Jeon, Seoul National University of Science and Technology

August 4, 2025

Advanced Optical Integration Processes for Photonic-Integrated Circuit Packaging

By Keuntae Baek, Hanyang University

August 4, 2025

Fast and Accurate Jitter Modeling for Statistical BER Analysis for Chiplet Interconnect and Beyond

By Shenggao Li, TSMC

August 2, 2025

A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration

By Wei-Hsing Huang, Georgia Institute of Technology

July 31, 2025

ChipletPart: Scalable Cost-Aware Partitioning for 2.5D Systems

By Alexander Graening, University of California

July 29, 2025