Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity

By Emad Haque ¹, Pragnya Sudershan Nalla ², Jeff Zhang ¹, Sachin S. Sapatnekar ², Chaitali Chakrabarti ¹ and Yu Cao ^2
1 School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ 85282, USA 
² Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455, USA

Abstract

The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction of larger-scale VLSI systems with higher energy efficiency in data movement. However, conventional I/O circuitry, including electrostatic discharge (ESD) protection and signaling, introduces significant area overhead. Prior studies have identified this overhead as a major constraint in reducing chiplet size below 100 mm2. In this study, we revisit reliability requirements from the perspective of chiplet interface design. Through parasitic extraction and SPICE simulations, we demonstrate that ESD protection and inter-chiplet signaling can be substantially simplified in future 2.5D/3D packaging technologies. Such simplification, in turn, paves the road for further chiplet miniaturization and improves the composability and reusability of tiny chiplets.

To read the full article, click here