3D optoelectronics and co-packaged optics: when solving the wrong problems stalls deployment
April 1, 2026
Chiplet Technical Papers
Expert Streaming: Accelerating Low-Batch MoE Inference via Multi-chiplet Architecture and Dynamic Expert Trajectory Scheduling
March 31, 2026
WarPGNN: A Parametric Thermal Warpage Analysis Framework with Physics-aware Graph Neural Network
March 26, 2026
DUET: Disaggregated Hybrid Mamba-Transformer LLMs with Prefill and Decode-Specific Packages
March 25, 2026
DS2SC-Agent: A Multi-Agent Automated Pipeline for Rapid Chiplet Model Generation
March 25, 2026
In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Directions
March 24, 2026
ODIN-Based CPU-GPU Architecture with Replay-Driven Simulation and Emulation
March 23, 2026
Chipmunq: Fault-Tolerant Compiler for Chiplet Quantum Architectures
March 18, 2026
LEXI: Lossless Exponent Coding for Efficient Inter-Chiplet Communication in Hybrid LLMs
March 17, 2026
Link Quality Aware Pathfinding for Chiplet Interconnects
March 13, 2026
Effects of Poor Workload Partitioning on System Performance for Chiplet-Based Systems
March 13, 2026
Mozart: Modularized and Efficient MoE Training on 3.5D Wafer-Scale Chiplet Architectures
March 10, 2026
Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding
March 6, 2026
CarbonPATH: Carbon-aware pathfinding and architecture optimization for chiplet-based AI systems
March 5, 2026
RPU -- A Reasoning Processing Unit
March 5, 2026
Spatiotemporal thermal characterization for 3D stacked chiplet systems based on transient thermal simulation
March 2, 2026
Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs
February 24, 2026
Scope: A Scalable Merged Pipeline Framework for Multi-Chip-Module NN Accelerators
February 20, 2026
Scaling Routers with In-Package Optics and High-Bandwidth Memories
February 18, 2026
TDPNavigator-Placer: Thermal- and Wirelength-Aware Chiplet Placement in 2.5D Systems Through Multi-Agent Reinforcement Learning
February 16, 2026
