Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond

By Paul Scheffler ¹, Thomas Benz ¹, Tim Fischer ¹, Lorenzo Leone ¹, Sina Arjmandpour ¹, Luca Benini ^1,2
1 Integrated Systems Laboratory, ETH Zurich, Switzerland
² Department of Electrical, Electronic, and Information Engineering, University of Bologna, Italy

Abstract

We present a roadmap for open-source chiplet-based RISC-V systems targeting high-performance computing and artificial intelligence, aiming to close the performance gap to proprietary designs. Starting with Occamy, the first open, silicon-proven dual-chiplet RISC-V manycore in 12nm FinFET, we scale to Ramora, a mesh-NoC-based dual-chiplet system, and to Ogopogo, a 7nm quad-chiplet concept architecture achieving state-of-the-art compute density. Finally, we explore possible avenues to extend openness beyond logic-core RTL into simulation, EDA, PDKs, and off-die PHYs.

Index Terms—Chiplets, RISC-V, HPC, NoC, AI, Machine Learning

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