Chiplet technology for large-scale trapped-ion quantum processors
By Bassem Badawi 1, Philip C. Holz 2, Michael Raffetseder 1, Nicolas Jungwirth 1, Juris Ulmanis 2, Hans-Joachim Quenzer 3, Dirk Kahler 3, Thomas Monz 1,2, and Philipp Schindler 1
1 University of Innsbruck, Institute of Experimental Physics, Austria
2 Alpine Quantum Technologies GmbH, Austria
3 Fraunhofer Institute for Silicon Technology ISIT, Germany

Abstract
Trapped ions are among the most promising platforms for realizing a large-scale quantum information processor. Current progress focuses on integrating optical and electronic components into microfabricated ion traps to allow scaling to large numbers of ion qubits. Most available fabrication strategies for such integrated processors employ monolithic integration of all processor components and rely heavily on CMOS-compatible semiconductor fabrication technologies that are not optimized for the requirements of a trapped-ion quantum processor. In this work, we present a modular approach in which the processor modules, called chiplets, have specific functions and are fabricated separately. The individual chiplets are then combined using heterogeneous integration techniques. This strategy opens up the possibility of choosing the optimal materials and fabrication technology for each of the chiplets, with a minimum amount of fabrication limitations compared to the monolithic approach. Chiplet technology furthermore enables novel processor functionalities to be added in a cost-effective, modular fashion by adding or modifying only a subset of the chiplets. We describe the design concept of a chiplet-based trapped-ion quantum processor and demonstrate the technology with an example of an integrated individual-ion addressing system for a ten-ion crystal. The addressing system emphasizes the modularity of the chiplet approach, combining a surface ion trap manufactured on a glass substrate with a silicon substrate carrying integrated waveguides and a stack of 3D-printed micro-optics, achieving diffraction-limited focal spots at the ion positions.
To read the full article, click here
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Technical Papers
- Optimizing Inter-chip Coupler Link Placement for Modular and Chiplet Quantum Systems
- Chipmunq: Fault-Tolerant Compiler for Chiplet Quantum Architectures
- Chipmunq: A Fault-Tolerant Compiler for Chiplet Quantum Architectures
- Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
Latest Technical Papers
- APEX: an Adaptive Photonic-Electronic Chiplet Interconnection Architecture for DNN Inference
- Formal Foundations for Known Good Reliable Die Screening in Chiplet-Based AI Systems-on-Chip
- Optimization of Test-Access Architectures and Test Scheduling for 2.5D/3D Integration
- Learning to Place Chiplets: A Multi-Objective Reinforcement Learning Approach
- ThAME: 3D Memory-Enabled Heterogeneous Accelerator for LLM Mixture of Experts