ATMPlace: Analytical Thermo-Mechanical-Aware Placement Framework for 2.5D-IC
By Qipan Wang, Tianxiang Zhu, Tianyu Jia , Yibo Lin , Runsheng Wang , Ru Huang
Peking University, China
Abstract
Rising demand in AI and automotive applications is accelerating 2.5D-IC adoption, with multiple chiplets tightly placed to enable high-speed interconnects and heterogeneous integration. As chiplet counts grow, traditional placement tools—limited by poor scalability and reliance on slow simulations—must evolve beyond wirelength minimization to address thermal and mechanical reliability, critical challenges in heterogeneous integration.
In this paper, we present ATMPlace, the first analytical placer for 2.5D-ICs that jointly optimizes wirelength, peak temperature, and operational warpage using physics-based compact models. It generates Pareto-optimal placements for systems with dozens of chiplets. Experimental results demonstrate superior performance: 146% and 52% geo-mean wirelength improvement over TAP-2.5D and TACPlace, respectively, with 3–13% lower temperature and 5–27% less warpage — all achieved ∼10× faster. The proposed framework is general and can be extended to enable fast, scalable, and reliable design exploration for next-generation 2.5D systems.
Index Terms — 2.5D-IC; Thermo-Mechanical Optimization; Chiplet Placement; Thermal Warpage
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