In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Directions
By Xunyu Li, Runyu Miao, Zijian Yue and Albert Wang
Department of Electrical and Computer Engineering, University of California, Riverside, USA
Abstract
Heterogeneous integration opens a pathway to three-dimensional chiplet-based microsystem chips. Electrostatic discharge reliability is a major challenge to future smart chips featuring rich functionalities and ultra performance, utilizing advanced heterogeneous integration and packaging technologies. This paper discusses emerging challenges and future research directions in developing robust electrostatic discharge protection solutions for future systems-on-integrated-chiplets.
Keywords: electrostatic discharge; ESD protection; chiplet; SoIC; heterogeneous integration
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