Link Quality Aware Pathfinding for Chiplet Interconnects
March 13, 2026
Chiplet Technical Papers
Effects of Poor Workload Partitioning on System Performance for Chiplet-Based Systems
March 13, 2026
Mozart: Modularized and Efficient MoE Training on 3.5D Wafer-Scale Chiplet Architectures
March 10, 2026
Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding
March 6, 2026
CarbonPATH: Carbon-aware pathfinding and architecture optimization for chiplet-based AI systems
March 5, 2026
RPU -- A Reasoning Processing Unit
March 5, 2026
Spatiotemporal thermal characterization for 3D stacked chiplet systems based on transient thermal simulation
March 2, 2026
Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs
February 24, 2026
Scope: A Scalable Merged Pipeline Framework for Multi-Chip-Module NN Accelerators
February 20, 2026
Scaling Routers with In-Package Optics and High-Bandwidth Memories
February 18, 2026
TDPNavigator-Placer: Thermal- and Wirelength-Aware Chiplet Placement in 2.5D Systems Through Multi-Agent Reinforcement Learning
February 16, 2026
Towards Scalable Multi-Chip Wireless Networks with Near-Field Time Reversal
February 11, 2026
Hybrid surface pre-treatments for enhancing copper-to-copper direct bonding
February 11, 2026
Toward Digital Twins in 3D IC Packaging: A Critical Review of Physics, Data, and Hybrid Architectures
February 4, 2026
Foundry-Enabled Patterning of Diamond Quantum Microchiplets for Scalable Quantum Photonics
February 3, 2026
Advances in waveguide to waveguide couplers for 3D integrated photonic packaging
January 30, 2026
Lifecycle Cost-Effectiveness Modeling for Redundancy-Enhanced Multi-Chiplet Architectures
January 28, 2026
DISTIL: A Distributed Spiking Neural Network Accelerator on 2.5D Chiplet Systems
January 27, 2026
Multi-Partner Project: COIN-3D -- Collaborative Innovation in 3D VLSI Reliability
January 22, 2026
EOTPR Fine Pitch Probing for Die-to-Die Interconnect Failure Analysis
January 21, 2026