Scope: A Scalable Merged Pipeline Framework for Multi-Chip-Module NN Accelerators By Zongle Huang, Tsinghua University February 20, 2026
Scaling Routers with In-Package Optics and High-Bandwidth Memories By Isaac Keslassy, Technion February 18, 2026
TDPNavigator-Placer: Thermal- and Wirelength-Aware Chiplet Placement in 2.5D Systems Through Multi-Agent Reinforcement Learning By Yubo Hou, A*STAR February 16, 2026
Towards Scalable Multi-Chip Wireless Networks with Near-Field Time Reversal By Ama Bandara, Universitat Politecnica de Catalunya February 11, 2026
Hybrid surface pre-treatments for enhancing copper-to-copper direct bonding By Wei-Ting Chen, National Chung Hsing University February 11, 2026
Toward Digital Twins in 3D IC Packaging: A Critical Review of Physics, Data, and Hybrid Architectures By Gourab Datta, University of Oklahoma February 4, 2026
Foundry-Enabled Patterning of Diamond Quantum Microchiplets for Scalable Quantum Photonics By Jawaher Almutlaq, Massachusetts Institute of Technology February 3, 2026
Advances in waveguide to waveguide couplers for 3D integrated photonic packaging By Drew Weninger, Massachusetts Institute of Technology January 30, 2026
Lifecycle Cost-Effectiveness Modeling for Redundancy-Enhanced Multi-Chiplet Architectures By Zizhen Liu, Chinese Academy of Sciences January 28, 2026
DISTIL: A Distributed Spiking Neural Network Accelerator on 2.5D Chiplet Systems By Pramit Kumar Pal, Washington State University January 27, 2026
Multi-Partner Project: COIN-3D -- Collaborative Innovation in 3D VLSI Reliability By George Rafael Gourdoumanis, University of Thessaly January 22, 2026
EOTPR Fine Pitch Probing for Die-to-Die Interconnect Failure Analysis By Bernice Zee, Advanced Micro Devices January 21, 2026
InterPUF: Distributed Authentication via Physically Unclonnable Functions and Multi-party Computation for Reconfigurable Interposers By Ishraq Tashdid, University of Central Florida January 20, 2026
Thermal stability enhancement of low temperature Cu-Cu bonding using metal passivation technology for advanced electronic packaging By Mu-Ping Hsu, National Yang Ming Chiao Tung University January 19, 2026
Development and Optimization of Fine-Pitch RDL for RDL Interposer, and Embedded Bridge Die Interposer Fabrication Using Fan-Out Wafer-Level Packaging Technology By Jung Won Lee, Nepes Corporation January 13, 2026
Thermo-mechanical co-design of 2.5D flip-chip packages with silicon and glass interposers via finite element analysis and machine learning By Mohammad Rafiee, University of Ottawa January 7, 2026
High-Efficient and Fast-Response Thermal Management by Heterogeneous Integration of Diamond on Interposer-Based 2.5D Chiplets By Ningning Xu, Xiamen University January 5, 2026
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement By Patrick Iff, ETH Zurich January 5, 2026
A physics-constrained and data-driven approach for thermal field inversion in chiplet-based packaging By Yupeng Qi, Shanghai University December 30, 2025