Issues In Ramping Advanced Packaging
Multi-die assemblies require significantly more test data than a monolithic chip. Thermal mismatch between different layers can cause warping, which puts stress on the bonds that connect those layers, resulting in failures during testing. The big problem is that traditional daisy-chained test approaches cannot pinpoint where problems are occurring. Instead, they provide a go/no-go for the entire system. Jack Lewis, chief technologist at Modus Test, talks with Semiconductor Engineering about how to obtain data at critical points, how to isolate it from other data, and how much data is required to identify real and latent defects.
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
Related Videos
- Onshoring Advanced Packaging in the United States
- GENIOEVO™ – Architectural Exploration and Connectivity Management in Advanced Packaging
- Propelling AI forward through Advanced Packaging Creativity
- Advanced Packaging & Chiplet Design with Chipletz
Latest Videos
- Accelerating Chiplet SoC Development with Standards-Based Frameworks and Automated Design Flows
- Qualcomm's Tony Pialis on Dragonfly and the Data Movement Wall
- From silos to system: Sujit Sharan on the cultural and technical shift 3D IC demands
- Advancing 3DIC Technologies to Propel AI Innovations
- Building Real Confidence in Chiplet Stacks with Evelyn Landman of proteanTecs