Proximity is all You Need – Two Tricks for Chiplet Interconnects

By Torsten Hoefler, ETH Zürich

As chiplet-based designs gain momentum, the challenge of optimizing topologies within technology and packaging constraints becomes ever more pressing. This talk explores two powerful techniques for improving chiplet interconnects developed under the lead of my student Patrick Iff while adhering to distance limitations imposed by various packaging technologies.

We begin with an overview of key packaging constraints and technologies, setting the foundation for an efficient chiplet network. We then introduce HexaMesh, an optimal tiling scheme designed to minimize diameter while maximizing bandwidth across chiplet architectures. Expanding on this, the brickwall arrangement is presented—enabling an innovative six-neighbor connectivity model to enhance performance beyond traditional four-neighbor topologies.

Building on HexaMesh, we demonstrate how Folded HexaTorus transforms the structure through slightly longer links, achieving symmetry (vertex transitivity) while dramatically reducing network diameter. These techniques pave the way for next-generation scalable chiplet architectures, ensuring both performance and manufacturability remain aligned with practical constraints.

Finally, we showcase RapidChiplet, a comprehensive toolchain designed for chiplet evaluation, simulation, and design space exploration. Through this framework, we empower engineers to analyze and optimize chiplet-based architectures efficiently, unlocking new levels of scalability and performance.

Join us as we navigate the future of chiplet interconnects, demonstrating how these techniques redefine the boundaries of scalable and high-bandwidth computing systems.