Cadence Chiplets Solutions: Helping you realize your chiplet ambitions

In this webinar, David Glasco, VP of Compute Solutions at Cadence, discusses how Cadence enables customers to transition from traditional monolithic SoC architectures to modular, scalable chiplet-based solutions, essential for meeting the growing demands of physical AI applications and high-performance computing.
 
Through a comprehensive suite of platforms, IP, tools, and design services that address every stage of the chiplet development process, see how Cadence helps customers realize their chiplet ambitions using:

• Cadence Chiplet Framework: A configurable hardware-software chiplet harness that enables interoperable chiplets through spec-based chiplet management, debug, NoC, connectivity and customizable functions.
• Reference Platforms: Provides silicon-proven frameworks and customizable reference designs for interconnects (e.g., UCIe), security, and system functions, reducing engineering effort, time-to-market, and design risks.
• Industry Standards: Collaborates with standards like Arm’s CSA, OCP’s FCSA, and UCIe to ensure interoperability and connectivity in multi-vendor ecosystems.
• Security Solutions: Offers end-to-end security, including secure boot, attestation, and lifecycle management, through our Secure-IC security solutions.
• Design Services & IP: Delivers world-class IP, EDA tools, and expert design services for diverse applications, enabling scalable, cost-effective chiplet solutions.

 Learn about the 4Cs of chiplets: Cost efficiency, customization, configurability, and the Cadence Technology Ecosystem to optimize costs, reduce engineering risks, and accelerate time-to-market.