Standards for Chiplet Design with 3DIC Packaging - Part 2
The goal of the workshop is to identify standards that, if developed, can simplify chiplet/3DIC design from specification and tapeout to chip packaging. We envision that interoperable formats will streamline handoffs between design, verification, assembly and packaging tools. Standardized workflows will also facilitate collaboration across organizational boundaries.
Speakers
- OCP (ADK/MDK) - James Wong, OCP CDX Co-Lead
- Intel - Lalitha Immaneni, VP, Architecture, Design and Technology Advanced Packaging
- Anemoi Software - David Ratchkov, CEO and Founder, OCP CDX Co-Lead
- Synopsys - Aparna Tarde, Technical Marketing Manager
- ARM - Dominic Brown, Senior Prinicipal Engineer
- Fermilab - Farah Fahim, Division Director, Microelectronics
- Microchip - Anu Ramamurthy, Associate Fellow, Design
- UCLA - Puneet Gupta, Professor, Electrical and Computer Engineering
- Alphawave Semi - Sue Hung Fung, Product Marketing Manager
- Si2 - Marc Rose, Executive Technical Assistant
- Blue Cheetah - Elad Alon, CEO and Co-founder
- OCP - James Wong, OCP CDX Co-Lead
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
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- Standards for Chiplet Design with 3DIC Packaging (Part 1)
- Advanced Packaging & Chiplet Design with Chipletz
- Accelerating Chiplet Design with OCP Standards Compliant Chiplet Framework and Automation
- Cadence & Samsung: Chiplet Ecosystem Innovation for Edge AI | CadenceLive 2026
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