Synopsys Keynote at Chiplet Summit 2025: Accelerating AI Chip Development with 3D Multi-Die Designs
Abhijeet Chakraborty, VP Engineering at Synopsys, presented one of the keynotes at the 2025 Chiplet Summit. He talks about essential multi-die innovations need to build the latest artificial intelligence (AI) chips. He also touches on the necessary lifecycle management needs of developers
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- Accelerating Chiplet SoC Development with Standards-Based Frameworks and Automated Design Flows
- Accelerating AI Innovation with Arm Total Design: A Case Study
- Accelerate 3D IC designs with Innovator3D IC
- Accelerating Software Development for High Performance Chiplet-based Compute Using Virtual Prototype
Latest Videos
- Agile Silicon Will Open Chiplet Architectures Keep Pace with Fast-Evolving AI Dataflows
- One Abstraction, Many Transports: Push-Mode Communication from Chiplet to Rack
- Advancing Chiplet Flexibility Updates in 2.0 OCE Transaction and Link Layer Specification
- GTC '26 - Berlin | Long-running, multi-tool Fuse Agents for 3D IC workflows
- Securing the Open Chiplet Ecosystem Defining a Common Security Architecture for FCSA