Multi-Die Verification

Chiplets offer unprecedented flexibility in high-performance designs, but they also add new challenges on the verification side. Changing out a chiplet, or adding a new one, can mean having to re-verify an entire multi-die system, a problem that becomes even more complicated if those chiplets are developed by different vendors. Paul Graykowski, director of product marketing at Cadence Design Systems, talks with Semiconductor Engineering about how to divide and conquer verification while keeping everything in sync, how to leverage existing testbenches, and the impact of multi-die on performance testing.