The Great Verification Chiplet Challenge

Chiplet technology represents a paradigm shift in semiconductor design, heralding a new era of more modular and efficient approach to building complex systems-on-chip (SoCs). The latest trend racing through the semiconductor industry is the move to chiplets as companies are invigorating themselves to stay on the cutting edge of technology. Or so it seems as European and U.S. companies embrace a chiplet strategy to overcome Moore’s Law and continue boosting the performance of their latest devices. Overlooked in the heady rush to chiplets are necessary changes to verification to meet the interfacing requirements of a complex chiplet structure.

DVCon Europe presents “The Great Verification Chiplet Challenge” panel featuring Moderator Nick Flaherty who referees a free-form discussion to unravel the thorny questions about advancing verification to support chiplets and the emerging UCIe interconnect chiplets standard. Panelists from a cross-section of the chip and design verification community address the chiplet factor facing verification methodologies and why verification must expand beyond functional block tests. The panel explores strategies for comprehensive verification, including the role of simulation, emulation, and hardware/software co-verification in ensuring the reliability and functionality of chiplet-based systems.

Moderator: Nick Flaherty, Editor-in-Chief, eeNews Europe

Panelists:

• Axel Jahnke, Nokia
• Bodo Hoppe, IBM
• Ashish Darbari, Axiomise
• David Kelf, Breker Verification Systems
• Moshe Zalcberg, Veriest