Development and Optimization of Fine-Pitch RDL for RDL Interposer, and Embedded Bridge Die Interposer Fabrication Using Fan-Out Wafer-Level Packaging Technology

By Jung Won Lee ¹, Sung Hyuk Lee ¹, Jay Kim ¹, Lewis Kang ¹, Han Ju Yu ¹, Min Ji Lee ¹, Seong Hwan Han ¹, Jae Kyung Lee ¹, Hailey Hwang ¹, Jun Gi Kim ¹, Chan Young Hong ¹, Jade Park ¹, Su Hyun Kim ¹, Myeong Jin Kim ² and M. Kim ^3
1 Advanced Technology Development Part, Technology Development Division, SEMI R&D Center, nepes Corporation, Republic of Korea
² Technology Development Division, SEMI R&D Center, nepes Corporation, Republic of Korea
³ Department of Electronics Engineering, Kongju National University, Republic of Korea

Abstract

Chiplet technology enables the integration of heterogeneous dies into a single system, of-fering improved performance, scalability, and design flexibility. To support chiplet-based architectures, advanced packaging methods such as System-in-Package (SiP), 2.5D inter-posers, and 3D stacking are essential. A key enabler in these technologies is the fine-pitch Redistribution Layer (RDL), which ensures high interconnect density, signal integrity, and thermal efficiency. This study presents the development and optimization of fine-pitch RDL for two inter-poser types—2.5D RDL interposers and Embedded Bridge Die interposers—fabricated using fan-out wafer-level packaging (FOWLP). A newly developed positive photoresist was used in the photolithography process to define sub-micron RDL features. Process pa-rameters such as exposure energy and focus settings were systematically optimized to improve pattern resolution and structural integrity. Experimental results demonstrated that optimized lithographic conditions significantly enhanced the fidelity and uniformity of fine-pitch RDLs, enabling reliable signal trans-mission and manufacturability in multi-die systems. The findings confirm that fine-pitch RDL is a foundational technology for next-generation interposer solutions, supporting tighter die spacing and improved system performance. This technology can be imple-mented across various chiplet-based packaging platforms, such as those used in next generation artificial intelligence (AI) processors and high-performance computing (HPC) architectures.

Keywords: FOWLP (FanOut Wafer Level Package);  interposer;  chiplet;  advanced packaging;  fine pitch RDL

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