Wafer Warpage of Silicon Interposer in Manufacturing Processes for High Density 2.5D Advanced Packaging: Causes, Measurement, Analysis and Optimization

By Hanwen Cui ^a,b, Yanze Gao ^a,b, Bing Wu ^c, Zhaotian Li ^a,b, Yunyun Sun ^c, Zhiwen Chen ^a,b, Yikang Zhou ^d, Kai Zheng ^d, Zhiliang Xia ^e, Zongliang Huo ^e, Yuzheng Guo ^c, Ching-Ping Wong ^f, Sheng Liu ^a,b,c, Zhaofu Zhang ^a,b
a School of Integrated Circuits, Wuhan University, Wuhan, 430072, China
^b The Institute of Technological Sciences, Wuhan University, Wuhan, 430072, China
^c School of Power and Mechanical Engineering, Wuhan University, Wuhan, Hubei, 430072, China
^d Semiconductor Technology Innovation Center (Beijing) Corporation, Beijing, 100176, China
^e Yangtze Memory Technologies Co., Ltd, Wuhan 430205, China
^f School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, 30332, United States

Abstract

Chiplet packaging, as a core technology in advanced electronic packaging, aims to enhance chip integration density, performance density, and signal transmission efficiency while reducing power consumption, cost, and size. Silicon interposer, a representative technology of high density 2.5D packaging, which is an essential technology for chiplet architectures, enables collaborative operation of chips with different process nodes by integrating high density through-silicon vias and multi-layer redistribution layers. However, the manufacturing process of silicon interposer involves multiple materials with varying coefficients of thermal expansion and thermal processing steps, which are prone to causing significant wafer warpage, thereby affecting interposer yield and increasing costs. This review provides a comprehensive overview of the complete manufacturing processes of silicon interposer, with in-depth analysis of warpage evolution and mechanisms at each process stage, offering critical insights for engineers to understand interposer warpage. It systematically summarizes wafer warpage measurement techniques, predictive models, and optimization strategies, illustrating their practical implementation paths in controlling the wafer warpage. Additionally, this review highlights current technical challenges and potential solutions for further improving warpage control accuracy and presents forward-looking perspectives on future research directions in this field.

Keywords: Chiplet, Silicon interposer, Through-silicon via, Redistribution layer, Wafer warpage, Advanced packaging

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