Optimizing Data Movement in SoCs and Advanced Packages
Andy Nightingale from Arteris talks about the demand for low-latency on-chip communication in increasingly complex devices, which can include chiplets, multiple networks on chip (NoCs), and the need for managing all of this with less power and using a simpler setup.
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Videos
- Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive and Data Center Architectures
- Analyzing Packet Data Flow in Chiplet Based SoCs
- GENIOEVO™ – Architectural Exploration and Connectivity Management in Advanced Packaging
- Inside the AI Bottleneck: Data Movement, Chiplets, and System Scaling
Latest Videos
- From Transistors to AI: The Chiplet Revolution with Ramune Nagisetty
- Scaling AI with Chiplets & CPO
- Open Interconnect Innovations: A Deep Dive into the UALink Chiplet Specification Tutorial
- From chips to silicon destiny: The next wave of 3D IC
- How Chiplets are Helping to Democratize Semiconductor Design with Mohit Gupta, CEO of TYLsemi