Analyzing Packet Data Flow in Chiplet Based SoCs
By Honnappa Nagarahalli, Arm
CPU vendors have introduced chiplet based SoCs with several advantages. The chiplets within the SoCs are connected together with additional interconnects. These additional interconnects introduce additional latencies compared to monolithic SoCs. This session analyses the packet flow in a typical chiplet based SoC while using DPDK. It identifies the flows where the latencies are introduced. It will introduce solutions based on the features in Arm products implemented based on industry standards.
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- Optimizing Data Movement in SoCs and Advanced Packages
- UCIe Based Chiplet Ecosystem Interoperable Testbench for Multi Vendor IP Integration
- Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive and Data Center Architectures
- Chiplet based Reconfigurable OCP Accelerator Module (OAM) architecture and platform
Latest Videos
- Agile Silicon Will Open Chiplet Architectures Keep Pace with Fast-Evolving AI Dataflows
- One Abstraction, Many Transports: Push-Mode Communication from Chiplet to Rack
- Advancing Chiplet Flexibility Updates in 2.0 OCE Transaction and Link Layer Specification
- GTC '26 - Berlin | Long-running, multi-tool Fuse Agents for 3D IC workflows
- Securing the Open Chiplet Ecosystem Defining a Common Security Architecture for FCSA