Analyzing Packet Data Flow in Chiplet Based SoCs
By Honnappa Nagarahalli, Arm
CPU vendors have introduced chiplet based SoCs with several advantages. The chiplets within the SoCs are connected together with additional interconnects. These additional interconnects introduce additional latencies compared to monolithic SoCs. This session analyses the packet flow in a typical chiplet based SoC while using DPDK. It identifies the flows where the latencies are introduced. It will introduce solutions based on the features in Arm products implemented based on industry standards.
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Videos
- Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive and Data Center Architectures
- Optimizing Data Movement in SoCs and Advanced Packages
- UCIe Based Chiplet Ecosystem Interoperable Testbench for Multi Vendor IP Integration
- Inside the AI Bottleneck: Data Movement, Chiplets, and System Scaling
Latest Videos
- Inside the AI Bottleneck: Data Movement, Chiplets, and System Scaling
- On-Package Chiplet Innovations with UCIe
- Advanced Semiconductor Packaging Explained: Hybrid Bonding, Chiplets & Manufacturing Innovation
- The Chiplet Market Today and Where It's Headed
- Advanced Packaging & Chiplet Design with Chipletz