Analyzing Packet Data Flow in Chiplet Based SoCs
By Honnappa Nagarahalli, Arm
CPU vendors have introduced chiplet based SoCs with several advantages. The chiplets within the SoCs are connected together with additional interconnects. These additional interconnects introduce additional latencies compared to monolithic SoCs. This session analyses the packet flow in a typical chiplet based SoC while using DPDK. It identifies the flows where the latencies are introduced. It will introduce solutions based on the features in Arm products implemented based on industry standards.
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