Analyzing Packet Data Flow in Chiplet Based SoCs
By Honnappa Nagarahalli, Arm
CPU vendors have introduced chiplet based SoCs with several advantages. The chiplets within the SoCs are connected together with additional interconnects. These additional interconnects introduce additional latencies compared to monolithic SoCs. This session analyses the packet flow in a typical chiplet based SoC while using DPDK. It identifies the flows where the latencies are introduced. It will introduce solutions based on the features in Arm products implemented based on industry standards.
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Videos
- Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive and Data Center Architectures
- Optimizing Data Movement in SoCs and Advanced Packages
- UCIe Based Chiplet Ecosystem Interoperable Testbench for Multi Vendor IP Integration
- Charting Architectural Innovation in the Chiplet Era with OCP's Cliff Grossner
Latest Videos
- 2026 Predictions from Alpahwave Semi, now part of Qualcomm
- Arm Viewpoints: Chiplets explained – the technology and economics behind the next wave of silicon innovation
- The State of Multi-Die: Insights and Customer Requirements
- Coding approaches for increasing reliability and energy efficiency of 3D technologies
- AI-Driven Thermal Prediction for Enhanced Reliability in 3D HBM Chiplets