Open Interconnect Innovations: A Deep Dive into the UALink Chiplet Specification Tutorial
By Rob Pelt (AMD), Peter Onufryk (Intel), Swadesh Choudhary (Intel), Joe Wu (Intel), Gerald Pasdast (Intel)
Session chair: Shannon Kinkead (Sandia National Laboratories)
Open Interconnect Innovations: A Deep Dive into the UALink Chiplet Specification Tutorial presented by UALink and UCIe Consortia
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Videos
- What's New in UALink? Technical Deep Dive into the Latest UALink Specifications
- Introducing the UCIe™ 3.0 Specification: Continued Innovations in the Open Chiplet Ecosystem
- A Deep Dive into UCIe-3D
- UCIe 2.0 Specification: Advancing an open ecosystem for on-package chiplet innovation
Latest Videos
- Open Interconnect Innovations: A Deep Dive into the UALink Chiplet Specification Tutorial
- From chips to silicon destiny: The next wave of 3D IC
- How Chiplets are Helping to Democratize Semiconductor Design with Mohit Gupta, CEO of TYLsemi
- The Future of 3D Heterogeneous Integration (3DHI)
- Stop Guessing on Multi-Die PG Planning: Let AI Find the IR-Drop Sweet Spot