A Deep Dive into UCIe-3D
With increasing demands for higher performance, bandwidth density, and power efficiency the industry is rapidly adopting 2.5D and 3D packaging technologies to address these challenges. This shift highlights the pressing need for a unified industry ecosystem standard—one that provides a standardized architecture for streamlined manageability and addresses the unique design complexities of advanced packaging. The UCIe 2.0 specification supports 3D packaging – offering higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures.
Join us in this webinar as we dive into the benefits of UCIe-3D including its hybrid bonding optimization, flexible bump pitch adaptability, and the scalability needed to drive the next wave of chiplet and packaging innovations.
Presenter:
Zuoguo (Joe) Wu, UCIe Consortium Electrical Working Group Co-Chair and Sr Principal Engineer at Intel
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
Related Videos
- Open Interconnect Innovations: A Deep Dive into the UALink Chiplet Specification Tutorial
- What's New in UALink? Technical Deep Dive into the Latest UALink Specifications
- China Target Chiplet, will it be a shortcut for China semiconductor self sufficiency？
- China's Chiplet Revolution: A Game Changer in Semiconductor Industry
Latest Videos
- Accelerating Chiplet SoC Development with Standards-Based Frameworks and Automated Design Flows
- Qualcomm's Tony Pialis on Dragonfly and the Data Movement Wall
- From silos to system: Sujit Sharan on the cultural and technical shift 3D IC demands
- Advancing 3DIC Technologies to Propel AI Innovations
- Building Real Confidence in Chiplet Stacks with Evelyn Landman of proteanTecs