A Deep Dive into UCIe-3D
With increasing demands for higher performance, bandwidth density, and power efficiency the industry is rapidly adopting 2.5D and 3D packaging technologies to address these challenges. This shift highlights the pressing need for a unified industry ecosystem standard—one that provides a standardized architecture for streamlined manageability and addresses the unique design complexities of advanced packaging. The UCIe 2.0 specification supports 3D packaging – offering higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures.
Join us in this webinar as we dive into the benefits of UCIe-3D including its hybrid bonding optimization, flexible bump pitch adaptability, and the scalability needed to drive the next wave of chiplet and packaging innovations.
Presenter:
Zuoguo (Joe) Wu, UCIe Consortium Electrical Working Group Co-Chair and Sr Principal Engineer at Intel
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Videos
- China Target Chiplet, will it be a shortcut for China semiconductor self sufficiency？
- China's Chiplet Revolution: A Game Changer in Semiconductor Industry
- What's a Chiplet ? Why Now ?
- An EDA perspective on chips transforming into 3D systems
Latest Videos
- 2026 Predictions from Alpahwave Semi, now part of Qualcomm
- Arm Viewpoints: Chiplets explained – the technology and economics behind the next wave of silicon innovation
- The State of Multi-Die: Insights and Customer Requirements
- Coding approaches for increasing reliability and energy efficiency of 3D technologies
- AI-Driven Thermal Prediction for Enhanced Reliability in 3D HBM Chiplets