Accelerating Chiplet SoC Development with Standards-Based Frameworks and Automated Design Flows

Presenter: Derek McAulay, Design Engineering Architect, Cadence

As AI systems increase demand for high-performance and power-efficient silicon, chiplet architectures provide a scalable path to heterogeneous integration. This presentation introduces the Cadence Chiplet Framework, supporting Arm CSA, OCP FCSA, and UCIe standards, with pre-verified subsystems for control, security, safety, and debug. It also highlights SoC Cockpit, an automation platform using AI-assisted techniques to streamline development from architecture through RTL, verification, and implementation. Together, these technologies reduce engineering effort, accelerate development, and improve interoperability for complex multi-die SoC designs.