Introducing the UCIe™ 3.0 Specification: Continued Innovations in the Open Chiplet Ecosystem

The UCIe™ 3.0 Specification: Doubling Bandwidth, New Use Cases, and Enhanced Manageability for Scalable SiP Architectures

Aired: September 18, 2025 at 9:00 a.m. PT

The UCIe™ (Universal Chiplet Interconnect Express™) 3.0 specification was released in August 2025, doubling the data rates, delivering 48/64 GT/s speeds for UCIe-S and UCIe-A, to power next-gen multi-chip systems for evolving use cases, such as AI which continue to demand ever increasing bandwidth density, while maintaining low power.

This webinar will delve into the new features in the UCIe 3.0 specification including improvements to bandwidth density, power efficiency, enhanced manageability, and expanded design flexibility for scalable SiP architectures. The webinar will also cover new enhancements introduce in the UCIe 3.0 specification, such as runtime recalibration for improved power efficiency and extended sideband reach that supports more flexible multi-chip configurations. Additionally, the webinar will explore new manageability features like early firmware download and priority sideband packets increase system responsiveness and reliability.

Presenter: 
Dr. Debendra Das Sharma, UCIe Consortium Chairman, and Intel Senior Fellow and co-GM Memory and I/O Technologies, Intel Corporation