What's New in UALink? Technical Deep Dive into the Latest UALink Specifications
The UALink Consortium workgroup chairs explored the latest specifications and how UALink is meeting the escalating computing demands of AI.
Attendees learned about the technical objectives, key architectural enhancements, and implementation considerations for the following specifications:
- UALink Common Specification 2.0, including support for In-Network Compute
- UALink 200G Data Link/Physical Layer Specification 2.0
- UALink Manageability Specification 1.0
- UALink Chiplet Specification 1.0
Speakers: Derek Williams (AMD), Dave Brown (AMD), Justin King (AMD), Arun Satyanarayana (Google) and Rob Pelt (AMD)
0:00 UALink Common Specification 2.0 and In-Network Compute
18:42 UALink 200G Data Link/Physical Layer Specification 2.0
34:36 UALink Manageability Specification 1.0
54:52 UALink Chiplet Specification 1.0
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
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