Building an Interoperable Chiplet Ecosystem through Golden Die Validation with Pre Silicon Correlation

By Michael Klempa, Principal Engineer, Alphawave Semi and Pedro Merlo, Manager of Strategic Planning, Keysight Technologies

As AI, cloud, and HPC drive demand for disaggregated architectures, a robust, interoperable chiplet ecosystem is essential. This presentation introduces a framework centered on the UCIe standard and a novel “golden die methodology to validate chiplet interoperability. With no open-source golden die available, we demonstrate how existing UCIe IP can serve as a reference, using BIST and RAS features calibrated against known signals to verify link integrity. This enables compliance testing and supports scalable, multi-vendor integration. The framework also addresses a path towards compliance for beyond-224G connectivity leveraging D2D links. A detailed workflow is presented for characterizing TX, interconnect, and RX using calibrated test points and stress conditions, with results correlated to pre-silicon EDA simulations. This approach accelerates design cycles and enhances system reliability, paving the way for an open chiplet economy.