BoW PHY 2.1
By Kevin Donnelly (Eliyan), Kash Johal (Yorchip) and Shahab Ardalan (Enosemi)
The BoW working group is focused on extensions to the standard to expand its applications.
BoW.Optical. The co-integration of optical and electrical chiplet with a BoW interface not only reduces power consumption by utilizing direct-drive interfaces but also enables low-latency, distance-invariant I/O for any system, paving the way for the next generation of photonic-enabled systems.
BoW.Memory. With the growing needs of HPC and AI systems for Memory and low latency access, the “memory wall” is the limiting factor for performance. BoW.Memory will show how the BoW interface can be extended to improve BW/mm and be used to directly connect ASICs to Memory
BoW support for IoT and Wirebond. Key specs for this PHY are - low area, power, simplicity and flexibility. The goal is to support data rates of 1GHz down to 100Mhz. Wirebond devices and older technology nodes can now mix and match with more advanced BoW chiplets.
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- BoW 2.1 Enhancements for New Applications
- Unleashing Chiplet potential with BoW - "The Knot That Ties Chiplets Together"
- Keysight UCIe Chiplet PHY Designer Demo
- Keysight EDA Chiplet PHY Designer Demo
Latest Videos
- The European Chip Ecosystem
- Scaling up AI Compute, Memory and Connectivity
- CURIE: A Cycle-Accurate and Synthesizable UCIe Interface for the Agile Design and Co-Simulation of Chiplets
- Federated Chiplet Design and Simulation
- Custom HBM as a System: Co-designing the Base Die, Die to Die Power, and Package Thermals for AI Accelerators