BoW 2.1 Enhancements for New Applications
By Kevin Donnelly, VP, Eliyan and Morgan Whately, Distinguished Engineer, Infineon Technologies
During the last two decades, increases in compute performance in FLOPs has far outpaced the increases in memory bandwidth, leading to limitations in system performance often described as the Memory Wall. Many designers are considering die-to-die (D2D) interfaces like Bunch of Wires (BoW) to improve performance in ASIC-to-memory connections.
This talk review the BoW Memory Addendum to the BoW PHY 2.0 Specification, a new OCP contribution that is expected to be published before OCP Global Summit 2025.
The BoW Memory Addendum describes optional enhancements that enable the BoW D2D interface to more efficiently connect ASICs to memory device chiplets, providing improved performance at lower power than traditional off-package memory interfaces.
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