BoW 2.1 Enhancements for New Applications
By Kevin Donnelly, VP, Eliyan and Morgan Whately, Distinguished Engineer, Infineon Technologies
During the last two decades, increases in compute performance in FLOPs has far outpaced the increases in memory bandwidth, leading to limitations in system performance often described as the Memory Wall. Many designers are considering die-to-die (D2D) interfaces like Bunch of Wires (BoW) to improve performance in ASIC-to-memory connections.
This talk review the BoW Memory Addendum to the BoW PHY 2.0 Specification, a new OCP contribution that is expected to be published before OCP Global Summit 2025.
The BoW Memory Addendum describes optional enhancements that enable the BoW D2D interface to more efficiently connect ASICs to memory device chiplets, providing improved performance at lower power than traditional off-package memory interfaces.
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- BoW PHY 2.1
- Unleashing Chiplet potential with BoW - "The Knot That Ties Chiplets Together"
- UCIe Progress Report: Big Enhancements, IP Maturity, and Ecosystem Interoperability
- Blue Cheetah BlueLynx for Heterogeneous Integration: 16 Gbps Chiplet Interconnect IP for UCIe & BoW
Latest Videos
- The European Chip Ecosystem
- Scaling up AI Compute, Memory and Connectivity
- CURIE: A Cycle-Accurate and Synthesizable UCIe Interface for the Agile Design and Co-Simulation of Chiplets
- Federated Chiplet Design and Simulation
- Custom HBM as a System: Co-designing the Base Die, Die to Die Power, and Package Thermals for AI Accelerators