BoW 2.1 Enhancements for New Applications
By Kevin Donnelly, VP, Eliyan and Morgan Whately, Distinguished Engineer, Infineon Technologies
During the last two decades, increases in compute performance in FLOPs has far outpaced the increases in memory bandwidth, leading to limitations in system performance often described as the Memory Wall. Many designers are considering die-to-die (D2D) interfaces like Bunch of Wires (BoW) to improve performance in ASIC-to-memory connections.
This talk review the BoW Memory Addendum to the BoW PHY 2.0 Specification, a new OCP contribution that is expected to be published before OCP Global Summit 2025.
The BoW Memory Addendum describes optional enhancements that enable the BoW D2D interface to more efficiently connect ASICs to memory device chiplets, providing improved performance at lower power than traditional off-package memory interfaces.
Related Chiplet
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
Related Videos
- BoW PHY 2.1
- Unleashing Chiplet potential with BoW - "The Knot That Ties Chiplets Together"
- UCIe Progress Report: Big Enhancements, IP Maturity, and Ecosystem Interoperability
- Blue Cheetah BlueLynx for Heterogeneous Integration: 16 Gbps Chiplet Interconnect IP for UCIe & BoW
Latest Videos
- Zero trust in silicon: The new security imperative for chiplet-based 3D ICs
- Beyond the data pipe: Why connectivity IP is now the system-critical layer in every 3D IC
- An Automated Interconnect Modeling Framework for Rapid Cryptolet Design Space Exploration
- DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation
- The Evolution Of UCIe