Low-Loss Integration of High-Density Polymer Waveguides with Silicon Photonics for Co-Packaged Optics
By Jef Van Asch 1,2, Jeroen Missinne 1, Junwen He 2,3, Arnita Podpod 2, Guy Lepage 2, Negin Golshani 2, Rafal Magdziak 2, Huseyin Sar 2, Hakim Kobbi 2, Swetanshu Bipul 2, Dieter Bode 2, Yoojin Ban 2, Filippo Ferraro 2, Joris Van Campenhout 2 and Geert Van Steenberge 1
1 Centre for Microsystems Technology (CMST), imec and Ghent University, Technologiepark 126, 9052 Gent, Belgium
2 Imec, Kapeldreef 75, 3001 Leuven, Belgium
3 Currently at Huawei Technologies
Abstract
Co-Packaged Optics applications require scalable and high-yield optical interfacing solutions to silicon photonic chiplets, offering low-loss, broadband, and polarization-independent optical coupling while maintaining compatibility with widely used approaches for electrical redistribution. We present two heterogeneous integration techniques that enable high-density electrical and optical I/O connections, utilizing adiabatic coupling between on-chip silicon nitride (SiN) waveguides and package-level polymer optical waveguides. In the first approach, polymer waveguides are patterned using standard lithography directly on the surface of the photonic chip, ensuring compatibility with chip embedding as commonly employed in chip-first fanout wafer-level packaging. In the second approach, photonic chips are flip-chip bonded to the package substrate. Both techniques have been experimentally validated, achieving a coupling efficiency near 1 dB between SiN and polymer waveguides in O-band, for both TE and TM polarizations. SiN tapers were designed using the "Mono" method to optimize phase-matching conditions between the two waveguides, a critical requirement for integrating diverse optical components. These results demonstrate the potential of polymer waveguides in Co-Packaged Optics applications, achieving sub-2 dB chip-to-chip and chip-to-fiber coupling losses.
To read the full article, click here
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Technical Papers
- Interfacing silicon photonics for high-density co-packaged optics
- The Evolution of Photonic Integrated Circuits and Silicon Photonics
- A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration
- HALO: Memory-Centric Heterogeneous Accelerator with 2.5D Integration for Low-Batch LLM Inference
Latest Technical Papers
- APEX: an Adaptive Photonic-Electronic Chiplet Interconnection Architecture for DNN Inference
- Formal Foundations for Known Good Reliable Die Screening in Chiplet-Based AI Systems-on-Chip
- Optimization of Test-Access Architectures and Test Scheduling for 2.5D/3D Integration
- Learning to Place Chiplets: A Multi-Objective Reinforcement Learning Approach
- ThAME: 3D Memory-Enabled Heterogeneous Accelerator for LLM Mixture of Experts