Advanced Packaging and Chiplets Can Be for Everyone
By Boris Chau, Project Leader, Faraday Technology Corporation
EETimes (November 29, 2024)
The chiplet revolution is upon us. What began in laboratories as multi-die science projects has eventually evolved. A giant company like AMD, Intel or Nvidia can produce—either at TSMC or, in Intel’s case, internally—a giant, startlingly expensive CPU or GPU multi-die assembly using advanced packaging to achieve remarkable density, power efficiency and performance.
However, the real promise of chiplets is something different: to democratize the design of complex silicon systems so that even systems developers and small-fabless semiconductor companies could develop them.
Today, there are both promising signs and notable obstacles to this vision. But I believe it is already possible for a modest design team to achieve a chiplet-based design today. However, that requires a good understanding of the variables involved and how to manage these in delivering the final design. Very likely today, this will involve using an external partner with that expertise.
This advance cannot come too soon. As the package becomes a critical factor in system performance, integrating multiple semiconductor dies—often designed and manufactured by different companies—within the same package will be essential.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Technical Papers
- Material Needs and Measurement Challenges for Advanced Semiconductor Packaging: Understanding the Soft Side of Science
- Wafer Warpage of Silicon Interposer in Manufacturing Processes for High Density 2.5D Advanced Packaging: Causes, Measurement, Analysis and Optimization
- Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
- Intel Delivers Cutting-Edge Process Technologies to the Data Center with Intel 18A and Advanced Chiplet Packaging
Latest Technical Papers
- Failure Analysis in Transition: An Industry Survey of Challenges, Priorities, and Standardization Needs in Advanced Packaging and Heterogeneous Integration
- 2.5D Root of Trust: Securing the Chiplet Ecosystem
- Plasma Etch Process Optimization for Photonic-Grade Diamond-on-Insulator Substrates and Thickness Evaluation using Colorimetry
- CUTh-Solver: GPU-Accelerated Sparse Matrix Solver for High-Resolution Thermal Simulation of 3D ICs
- Making Locality-aware GEMM Compatible with Page-Granularity Placement on Chiplet GPUs