Fast and Accurate Jitter Modeling for Statistical BER Analysis for Chiplet Interconnect and Beyond
By Shenggao Li and Maher Amer (TSMC)
Abstract:
In this paper, we investigate Statistical Bit Error Rate (BER) analysis for low-loss short-reach chiplet interface and high-loss long-reach serial interface. We used jitter filtering to account for the residue jitter not tracked by a forwarded clock system and proposed a fast and exact Statistical BER method to account for the Tx jitter amplification effect in a high-loss channel. Our proposed method achieves a linear computation complexity.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Technical Papers
- ATSim: A Fast and Accurate Simulation Framework for 2.5D/3D Chiplet Thermal Design Optimization
- 3D-ICE 4.0: Accurate and efficient thermal modeling for 2.5D/3D heterogeneous chiplet systems
- Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging
- Fault Modeling, Testing, and Repair for Chiplet Interconnects
Latest Technical Papers
- Scope: A Scalable Merged Pipeline Framework for Multi-Chip-Module NN Accelerators
- Scaling Routers with In-Package Optics and High-Bandwidth Memories
- TDPNavigator-Placer: Thermal- and Wirelength-Aware Chiplet Placement in 2.5D Systems Through Multi-Agent Reinforcement Learning
- Towards Scalable Multi-Chip Wireless Networks with Near-Field Time Reversal
- Hybrid surface pre-treatments for enhancing copper-to-copper direct bonding