The multiphysics challenges of 3D IC designs

By John Ferguson, Siemens 
EETimes (August 9, 2024)

The semiconductor industry has integrated ever more functionality into smaller footprints and is starting to build upward. With the rise of three-dimensional integrated circuits (3D ICs), designers can pack more processing power and functionality into smaller spaces. However, this new dimension brings with it a host of challenges, including mechanical stresses and thermal effects, that affect electrical behavior.  

In traditional IC or system-on-chip (SoC) designs, these impacts are largely safeguarded by the fact that all devices are on a common silicon die. With a few appropriate design rules to keep devices sufficiently separated from local impacts, designers can ensure that most impacts are minimized or avoided. Simply by extracting some additional device parameters, further gross deficiencies can be flagged for review, enabling any additional concerns to be captured during post-layout simulation. Unfortunately, when it comes to the world of 3D IC design, those safe-guards are no longer practical. 

Unlike traditional ICS, 3D ICs stack multiple individual chiplets, which can be built on with different process nodes and interconnected using vertical interconnect accesses (vias), to create a single, compact package.

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